Flip-flops may refer to sequential circuits that store either a “high” value (voltage high or logic one) or a “low” value (voltage low or logic zero). A flip-flop may store a next value that depends on the values of one or more input signals. Conventionally, a flip-flop may include data, clock, set, and/or reset input signals.
A Data (conventionally designated D) input signal is typically clocked into the flip-flop on receipt of a given clock edge. Set (conventionally designated S) and Reset (conventionally designated R) input signals are generally unclocked, meaning that when the set or reset signal becomes active (e.g., goes high), the stored value changes immediately, without waiting for the arrival of a clock edge. Flop is usually a master-slave latch structure. Each latch is active (transparent) during either logic high or logic low phase (not edge). At the rising (trigger) edge, the master latch will latch the input and store the data value, the slave latch will become active (transparent) and pass the value to the output. Assume the active phase for the master latch is 0, then at the falling edge, maser latch will become active (transparent) to accept the next value and slave latch will latch what was latched by the master latch to continue output the value that was stored in the master latch. So output will change only at each triggering edge. An active set signal forces the stored value (conventionally designated Q) high, despite the previously stored value. An active reset signal forces the stored value Q low, despite the previously stored value. In set/reset flip-flops (i.e., flip-flops having both set and reset input signals) the set and reset signals are typically restricted such that at most one of them can be active at any given time. Since flip-flop is a fundamental building block of modern digital designs, there is always a need to minimize its power consumption and area. A flop-flop design is proposed that would reduce its power consumption and area compared to conventional designs.